An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC
	Zhu, XB (Zhu, Xubin); Ni, WN (Ni, Weining); Zhang, Q (Zhang, Qiang); Shi, Y (Shi, Yin); Zhu, XB, Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China.
	2007
会议名称	International Workshop on Electron Devices and Semiconductor Technology
会议录名称	2007 International Workshop on Electron Devices and Semiconductor Technology
页码	165-168
会议日期	JUN 03-04, 2007
会议地点	Beijing, PEOPLES R CHINA
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	978-1-4244-1097-2
部门归属	chinese acad sci, inst semicond, beijing 100083, peoples r china
摘要	This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.
关键词	Analog-to-digital Converter Cmos Analog Integrated Circuit Folding-and-interpolating Cascading
学科领域	人工智能
主办者	IEEE Electron Devices Soc. Tsinghua Univ
收录类别	CPCI-S
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/9828
专题	中国科学院半导体研究所（2009年前）
通讯作者	Zhu, XB, Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China.
推荐引用方式 GB/T 7714	Zhu, XB ,Ni, WN ,Zhang, Q ,et al. An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2007:165-168.

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