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题名: A Synthesis Tool for a Tile-Based Heterogeneous FPGA
作者: Zhang K;  Yu HM;  Chen SL;  Liu ZL
出版日期: 2008
会议日期: OCT 20-23, 2008
摘要: A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.
会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology
会议文集: 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY
专题: 中国科学院半导体研究所(2009年前)_会议论文

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推荐引用方式:
Zhang, K;Yu, HM;Chen, SL;Liu, ZL.A Synthesis Tool for a Tile-Based Heterogeneous FPGA .见:IEEE .2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY,345 E 47TH ST, NEW YORK, NY 10017 USA ,2008,VOLS 1-4: 2321-2324
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