Low power design in 100 MHz embedded SRAM

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	Low power design in 100 MHz embedded SRAM
	Wang DH; Qiu J; Li YG; Hou CH; Wang DH Chinese Acad Sci Inst Semicond POB 912 Beijing 100083 Peoples R China.
	2001
会议名称	4th International Conference on ASIC
会议录名称	2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS
页码	599-602
会议日期	OCT 23-25, 2001
会议地点	SHANGHAI, PEOPLES R CHINA
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	0-7803-6677-8
部门归属	chinese acad sci, inst semicond, beijing 100083, peoples r china
摘要	Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time.
学科领域	微电子学
主办者	Chinese Inst Electr.; IEEE Beijing Sect.; Natl Nat Sci Fdn China.; Shanghai Municipal Sci & Technol Commiss.
收录类别	CPCI-S
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/13685
专题	中国科学院半导体研究所（2009年前）
通讯作者	Wang DH Chinese Acad Sci Inst Semicond POB 912 Beijing 100083 Peoples R China.
推荐引用方式 GB/T 7714	Wang DH,Qiu J,Li YG,et al. Low power design in 100 MHz embedded SRAM[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2001:599-602.