A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

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	A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer
	Yan XZ (Yan Xiaozhou); Kuang XF (Kuang Xiaofei); Wu NJ (Wu Nanjian)
	2009
会议名称	IEEE International Symposium on Circuits and Systems (ISCAS 2009)
会议录名称	ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
页码	1525-1528
会议日期	MAY 24-27, 2009
会议地点	Taipei, TAIWAN
合作性质	其它
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	978-1-4244-3827-3
摘要	This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.
学科领域	微电子学
收录类别	CPCI（ISTP）
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/11197
专题	中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Yan XZ ,Kuang XF ,Wu NJ . A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2009:1525-1528.

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