Knowledge Management System Of Institute of Semiconductors,CAS
| A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit | |
| Kuang, XF; Wu, NJ; Shou, GL; Kuang, XF, Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, POB 912, Beijing 100083, Peoples R China. | |
| 2006 | |
| Conference Name | International Conference on Solid State Devices and Materials ( |
| Source Publication | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS |
| Pages | 45 (4B): 3290-3294 |
| Conference Date | SEP 13-15, 2005 |
| Conference Place | Kobe, JAPAN |
| Publication Place | 5F YUSHIMA BLDG, 2-31-22 YUSHIMA, BUNKYO-KU, TOKYO, 113-0034, JAPAN |
| Publisher | INST PURE APPLIED PHYSICS |
| ISSN | 0021-4922 |
| metadata_83 | chinese acad sci, inst semicond, state key lab superlattices & microstruct, beijing 100083, peoples r china; liuhewantong microelect ltd, beijing 100085, peoples r china |
| Abstract | This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature. |
| Keyword | Lock-in Speed |
| Subject Area | 半导体物理 |
| Funding Organization | Japan Soc Appl Phys & Tech.; IEEE Elect Devices Soc. |
| Indexed By | 其他 |
| Language | 英语 |
| Document Type | 会议论文 |
| Identifier | http://ir.semi.ac.cn/handle/172111/10024 |
| Collection | 中国科学院半导体研究所（2009年前） |
| Corresponding Author | Kuang, XF, Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, POB 912, Beijing 100083, Peoples R China. |
| Recommended Citation GB/T 7714 | Kuang, XF,Wu, NJ,Shou, GL,et al. A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit[C]. 5F YUSHIMA BLDG, 2-31-22 YUSHIMA, BUNKYO-KU, TOKYO, 113-0034, JAPAN:INST PURE APPLIED PHYSICS,2006:45 (4B): 3290-3294. |
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| 2395.pdf（169KB） | 限制开放 | -- | Application Full Text | |||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment