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题名: A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors
作者: Zhang WC (Zhang Wancheng);  Wu NH (Wu Nan-Han)
发表日期: 2007
摘要: This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.
刊名: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
专题: 中国科学院半导体研究所(2009年前)_期刊论文

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推荐引用方式:
Zhang, WC (Zhang, Wancheng); Wu, NH (Wu, Nan-Han) .A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors ,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,NOV 2007,54 (11):2516-2527
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