A Synthesis Tool for a Tile-Based Heterogeneous FPGA
Zhang K; Yu HM; Chen SL; Liu ZL; Zhang, K, Chinese Acad Sci, Inst Semicond, Beijing 10083, Peoples R China.
2008
会议名称9th International Conference on Solid-State and Integrated-Circuit Technology
会议录名称2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY
页码VOLS 1-4: 2321-2324
会议日期OCT 20-23, 2008
会议地点Beijing, PEOPLES R CHINA
出版地345 E 47TH ST, NEW YORK, NY 10017 USA
出版者IEEE
ISBN978-1-4244-2185-5
部门归属[zhang, kun; yu, hongmin; chen, stanley l.; liu, zhongli] chinese acad sci, inst semicond, beijing 10083, peoples r china
摘要A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.
学科领域微电子学
主办者IEEE Beijing Sect.; Chinese Inst Elect.; IEEE Electron Devices Soc.; IEEE EDS Beijing Chapter.; IEEE Solid State Circuits Soc.; IEEE Circuites & Syst Soc.; IEEE Hong Kong EDS, SSCS Chapter.; IEEE SSCS Beijing Chapter.; Japan Soc Appl Phys.; Elect Div IEEE.; URSI Commiss D.; Inst Elect Engineers Korea.; Assoc Asia Pacific Phys Soc.; Peking Univ, IEEE EDS Student Chapter.
收录类别其他
语种英语
文献类型会议论文
条目标识符http://ir.semi.ac.cn/handle/172111/8306
专题中国科学院半导体研究所(2009年前)
通讯作者Zhang, K, Chinese Acad Sci, Inst Semicond, Beijing 10083, Peoples R China.
推荐引用方式
GB/T 7714
Zhang K,Yu HM,Chen SL,et al. A Synthesis Tool for a Tile-Based Heterogeneous FPGA[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2008:VOLS 1-4: 2321-2324.
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