SEMI OpenIR  > 高速电路与神经网络实验室
并行可配置浮点矩阵乘法IP核设计
乔瑞秀; 鲁华祥; 龚国良; 陈刚
2015-11
Source Publication网络新媒体技术
Volume4Issue:6Pages:32-36
Keyword系统设计 Ip 核 浮点数运算 矩阵乘法
Subject Area智能系统的硬件化实现
Date Available2016-05-30
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/27081
Collection高速电路与神经网络实验室
Corresponding Author鲁华祥
Recommended Citation
GB/T 7714
乔瑞秀,鲁华祥,龚国良,等. 并行可配置浮点矩阵乘法IP核设计[J]. 网络新媒体技术,2015,4(6):32-36.
APA 乔瑞秀,鲁华祥,龚国良,&陈刚.(2015).并行可配置浮点矩阵乘法IP核设计.网络新媒体技术,4(6),32-36.
MLA 乔瑞秀,et al."并行可配置浮点矩阵乘法IP核设计".网络新媒体技术 4.6(2015):32-36.
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