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A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network
Shi, C; Yang, J; Han, Y; Cao, ZX; Qin, Q; Liu, LY; Wu, NJ; Wang, ZH
2014
Source PublicationIEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume49Issue:9Pages:2067-2082
Subject Area半导体物理
Indexed BySCI
Language英语
Date Available2015-03-25
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/26214
Collection半导体超晶格国家重点实验室
Recommended Citation
GB/T 7714
Shi, C,Yang, J,Han, Y,et al. A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS,2014,49(9):2067-2082.
APA Shi, C.,Yang, J.,Han, Y.,Cao, ZX.,Qin, Q.,...&Wang, ZH.(2014).A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.IEEE JOURNAL OF SOLID-STATE CIRCUITS,49(9),2067-2082.
MLA Shi, C,et al."A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network".IEEE JOURNAL OF SOLID-STATE CIRCUITS 49.9(2014):2067-2082.
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