An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

	An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags
	Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin and Liu Su
	2013
Source Publication	Journal of Semiconductors
Volume	34 Issue:8 Pages:085004
Subject Area	半导体物理
Indexed By	EI
Language	英语
Date Available	2014-05-08
Document Type	期刊论文
Identifier	http://ir.semi.ac.cn/handle/172111/24921
Collection	半导体超晶格国家重点实验室
Recommended Citation GB/T 7714	Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin and Liu Su. An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags[J]. Journal of Semiconductors,2013,34(8):085004.
APA	Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin and Liu Su.(2013).An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags.Journal of Semiconductors,34(8),085004.
MLA	Jia Xiaoyun,Feng Peng,Zhang Shengguang,Wu Nanjian,Zhao Baiqin and Liu Su."An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags".Journal of Semiconductors 34.8(2013):085004.

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