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Design and optimization of a2.4 GHz RF front-end with an on-chip balun
Xu, Hua; Wang, Lei; Shi, Yin; Dai, Fa Foster; Xu, H.(hxu@semi.ac.cn)
2011
Source PublicationJournal of Semiconductors
ISSN16744926
Volume32Issue:9Pages:95004
AbstractA2.4 GHz low-power, low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for the best noise performance of the front-end. The circuit is implemented with0.35μm SiGe BiCMOS technology. The front-end has three gain steps for maximization of the input dynamic range. The overall maximum gain is about36 dB. The double-sideband noise figure is3.8 dB in high gain mode and the input referred third-order intercept point is12.5 dBm in low gain mode. The down-conversion mixer has a tunable parallel R- C load at the output and an emitter follower is used as the output stage for testing purposes. The total front-end dissipation is33 mW under a2.85 V supply and occupies a0.66 mm2 die size.?2011 Chinese Institute of Electronics.
metadata_83高性能集成电路实验室
KeywordBicmos Technology Load Testing Mixers(Machinery) Optimization Semiconducting Silicon
Subject Area微电子学
Indexed ByEI
Date Available2012-06-14
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/23077
Collection高性能集成电路实验室
Corresponding AuthorXu, H.(hxu@semi.ac.cn)
Recommended Citation
GB/T 7714
Xu, Hua,Wang, Lei,Shi, Yin,et al. Design and optimization of a2.4 GHz RF front-end with an on-chip balun[J]. Journal of Semiconductors,2011,32(9):95004.
APA Xu, Hua,Wang, Lei,Shi, Yin,Dai, Fa Foster,&Xu, H..(2011).Design and optimization of a2.4 GHz RF front-end with an on-chip balun.Journal of Semiconductors,32(9),95004.
MLA Xu, Hua,et al."Design and optimization of a2.4 GHz RF front-end with an on-chip balun".Journal of Semiconductors 32.9(2011):95004.
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