Knowledge Management System Of Institute of Semiconductors,CAS
| High speed CMOS vision chips | |
| Wu, Nanjian; Wu, N.(nanjian@red.semi.ac.cn) | |
| 2011 | |
| Source Publication | Midwest Symposium on Circuits and Systems
 |
| ISSN | 15483746 |
| Pages | 6026285 |
| Abstract | This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements(PEs) and a column of SIMD row processors(RPs). The PE array and RPs have an O(NxN) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.?2011 IEEE. |
| metadata_83 | 半导体超晶格国家重点实验室 |
| Keyword | Cmos Integrated Circuits Computer Vision Image Recognition Target Tracking |
| Subject Area | 半导体物理 |
| Indexed By | EI |
| Date Available | 2012-06-14 |
| Document Type | 期刊论文 |
| Identifier | http://ir.semi.ac.cn/handle/172111/23055 |
| Collection | 半导体超晶格国家重点实验室 |
| Corresponding Author | Wu, N.(nanjian@red.semi.ac.cn) |
| Recommended Citation GB/T 7714 | Wu, Nanjian,Wu, N.. High speed CMOS vision chips[J]. Midwest Symposium on Circuits and Systems,2011:6026285. |
| APA | Wu, Nanjian,&Wu, N..(2011).High speed CMOS vision chips.Midwest Symposium on Circuits and Systems,6026285. |
| MLA | Wu, Nanjian,et al."High speed CMOS vision chips".Midwest Symposium on Circuits and Systems (2011):6026285. |
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| High speed CMOS visi（1064KB） | 限制开放 | License | Application Full Text | |||
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