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High speed CMOS vision chips
Wu, Nanjian; Wu, N.(
Source PublicationMidwest Symposium on Circuits and Systems
AbstractThis paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements(PEs) and a column of SIMD row processors(RPs). The PE array and RPs have an O(NxN) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.?2011 IEEE.
KeywordCmos Integrated Circuits Computer Vision Image Recognition Target Tracking
Subject Area半导体物理
Indexed ByEI
Date Available2012-06-14
Document Type期刊论文
Corresponding AuthorWu, N.(
Recommended Citation
GB/T 7714
Wu, Nanjian,Wu, N.. High speed CMOS vision chips[J]. Midwest Symposium on Circuits and Systems,2011:6026285.
APA Wu, Nanjian,&Wu, N..(2011).High speed CMOS vision chips.Midwest Symposium on Circuits and Systems,6026285.
MLA Wu, Nanjian,et al."High speed CMOS vision chips".Midwest Symposium on Circuits and Systems (2011):6026285.
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