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Current reusing low power fast settling multi-standard CMOS fractional-N frequency synthesizer | |
Lou, Wenfeng; Feng, Peng; Wu, Nanjian; Lou, W. | |
2011 | |
Source Publication | 2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT2011
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Pages | 129-132 |
Abstract | A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practice application. This PLL is implemented in a0.18um technology. The frequency range is0.3GHz to2.54GHz and the settling time is less than5us over the entire frequency range. It consumes only4.35mA@1.8V.?2011 IEEE. |
metadata_83 | 半导体超晶格国家重点实验室 |
Keyword | Frequency Synthesizers Phase Locked Loops |
Subject Area | 半导体物理 |
Indexed By | EI |
Language | 英语 |
Date Available | 2012-06-14 |
Document Type | 期刊论文 |
Identifier | http://ir.semi.ac.cn/handle/172111/23049 |
Collection | 半导体超晶格国家重点实验室 |
Corresponding Author | Lou, W. |
Recommended Citation GB/T 7714 | Lou, Wenfeng,Feng, Peng,Wu, Nanjian,et al. Current reusing low power fast settling multi-standard CMOS fractional-N frequency synthesizer[J]. 2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT2011,2011:129-132. |
APA | Lou, Wenfeng,Feng, Peng,Wu, Nanjian,&Lou, W..(2011).Current reusing low power fast settling multi-standard CMOS fractional-N frequency synthesizer.2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT2011,129-132. |
MLA | Lou, Wenfeng,et al."Current reusing low power fast settling multi-standard CMOS fractional-N frequency synthesizer".2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT2011 (2011):129-132. |
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2012062.pdf(377KB) | 限制开放 | License | Application Full Text |
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