SEMI OpenIR  > 半导体超晶格国家重点实验室
A Programmable Vision Chip Based on Multiple Levels of Parallel Processors
Zhang WC; Fu QY; Wu NJ; Zhang, WC (reprint author), Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China, nanjian@red.semi.ac.cn
2011
Source PublicationIEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN0018-9200
Volume46Issue:9Pages:2132-2147
AbstractThis paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N x N) parallelism and an O(N) parallelism, respectively. The PE array and RPs can be reconfigured to handle algorithms with different complexities and processing speeds. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. The vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototype chip with 128 x 28 image sensor, 128 A/D converters, 32 8-bit RPs and 32 x 128 PEs is fabricated using the 0.18 mu m CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.
metadata_83半导体超晶格国家重点实验室
KeywordRecognition Systems Feature-extraction Image Sensor Architecture Design Array Vlsi
Subject Area半导体物理
Funding OrganizationNational Natural Science Foundation of China[60976023]; Chinese National High-Tech Researching and Development Projection[2008AA010703]; special funds for Major State Basic Research Project of China[2011CB932902]
Indexed BySCI
Language英语
Date Available2012-01-06
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/22665
Collection半导体超晶格国家重点实验室
Corresponding AuthorZhang, WC (reprint author), Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China, nanjian@red.semi.ac.cn
Recommended Citation
GB/T 7714
Zhang WC,Fu QY,Wu NJ,et al. A Programmable Vision Chip Based on Multiple Levels of Parallel Processors[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS,2011,46(9):2132-2147.
APA Zhang WC,Fu QY,Wu NJ,&Zhang, WC .(2011).A Programmable Vision Chip Based on Multiple Levels of Parallel Processors.IEEE JOURNAL OF SOLID-STATE CIRCUITS,46(9),2132-2147.
MLA Zhang WC,et al."A Programmable Vision Chip Based on Multiple Levels of Parallel Processors".IEEE JOURNAL OF SOLID-STATE CIRCUITS 46.9(2011):2132-2147.
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