Simulation of a Monolithic Integrated CMOS Preamplifier  for Neural Recordings

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings
	Sui Xiaohong; Liu Jinbin; Gu Ming; Pei Weihua; Chen Hongda
	2005
Source Publication	半导体学报
Volume	26 Issue:12 Pages:2275-2280
Abstract	A monolithic integrated CMOS preamplifier is presented for neural recording applications. Two AC-coupied capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface. Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier. A novel analysis is given to determine the noise power spectral density. Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVmax, integrated from 0. 1Hz to 1kHz. The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.
metadata_83	institute of semiconductors, chinese academy of sciences
Subject Area	光电子学
Funding Organization	国家高技术研究发展计划,国家自然科学基金资助项目
Indexed By	CSCD
Language	英语
CSCD ID	CSCD:2198522
Date Available	2010-11-23
Citation statistics
Document Type	期刊论文
Identifier	http://ir.semi.ac.cn/handle/172111/16815
Collection	中国科学院半导体研究所（2009年前）
Recommended Citation GB/T 7714	Sui Xiaohong,Liu Jinbin,Gu Ming,et al. Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings[J]. 半导体学报,2005,26(12):2275-2280.
APA	Sui Xiaohong,Liu Jinbin,Gu Ming,Pei Weihua,&Chen Hongda.(2005).Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings.半导体学报,26(12),2275-2280.
MLA	Sui Xiaohong,et al."Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings".半导体学报 26.12(2005):2275-2280.

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