SEMI OpenIR  > 中国科学院半导体研究所(2009年前)
A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node
Zhang Wancheng; Wu Nanjian
2008
Source Publication半导体学报
Volume29Issue:10Pages:1917-1921
AbstractThis paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator (SO1) technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic "1" while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable "read" operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin (SNM) of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
metadata_83institute of semiconductors, chinese academy of sciences
Subject Area微电子学
Funding Organization国家自然科学基金(批准号
Indexed ByCSCD
Language英语
CSCD IDCSCD:3399345
Date Available2010-11-23
Citation statistics
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/15943
Collection中国科学院半导体研究所(2009年前)
Recommended Citation
GB/T 7714
Zhang Wancheng,Wu Nanjian. A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node[J]. 半导体学报,2008,29(10):1917-1921.
APA Zhang Wancheng,&Wu Nanjian.(2008).A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node.半导体学报,29(10),1917-1921.
MLA Zhang Wancheng,et al."A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node".半导体学报 29.10(2008):1917-1921.
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