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题名: A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction
作者: Yan Xiaozhou;  Kuang Xiaofei;  Wu Nanjian
发表日期: 2009
摘要: This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.
刊名: 半导体学报
专题: 中国科学院半导体研究所(2009年前)_期刊论文

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推荐引用方式:
Yan Xiaozhou;Kuang Xiaofei;Wu Nanjian.A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction,半导体学报,2009,30(4):99-103
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