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题名: A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches
作者: Zhu Xubin;  Ni Weining;  Shi Yin
发表日期: 2009
摘要: A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
刊名: 半导体学报
专题: 中国科学院半导体研究所(2009年前)_期刊论文

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推荐引用方式:
Zhu Xubin;Ni Weining;Shi Yin.A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches,半导体学报,2009,30(5):109-112
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