SEMI OpenIR  > 中国科学院半导体研究所(2009年前)
Design for an IO block array in a tile-based FPGA
Ding Guangxin; Chen Lingdou; Liu Zhongli
2009
Source Publication半导体学报
Volume30Issue:8Pages:141-146
AbstractA design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.
metadata_83institute of semiconductors,chinese academy of sciences
Subject Area微电子学
Indexed ByCSCD
Language英语
CSCD IDCSCD:3657129
Date Available2010-11-23
Citation statistics
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/15721
Collection中国科学院半导体研究所(2009年前)
Recommended Citation
GB/T 7714
Ding Guangxin,Chen Lingdou,Liu Zhongli. Design for an IO block array in a tile-based FPGA[J]. 半导体学报,2009,30(8):141-146.
APA Ding Guangxin,Chen Lingdou,&Liu Zhongli.(2009).Design for an IO block array in a tile-based FPGA.半导体学报,30(8),141-146.
MLA Ding Guangxin,et al."Design for an IO block array in a tile-based FPGA".半导体学报 30.8(2009):141-146.
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