SEMI OpenIR  > 中国科学院半导体研究所(2009年前)
A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC
Yuan Ling; Ni Weining; Hao Zhikun; Shi Yin; Li Wenchang
2009
Source Publication半导体学报
Volume30Issue:9Pages:66-69
AbstractThis paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.
metadata_83institute of semiconductors, chinese academy of sciences;university of electronic science and technology of china
Subject Area人工智能
Indexed ByCSCD
Language英语
CSCD IDCSCD:3657151
Date Available2010-11-23
Citation statistics
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/15713
Collection中国科学院半导体研究所(2009年前)
Recommended Citation
GB/T 7714
Yuan Ling,Ni Weining,Hao Zhikun,et al. A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC[J]. 半导体学报,2009,30(9):66-69.
APA Yuan Ling,Ni Weining,Hao Zhikun,Shi Yin,&Li Wenchang.(2009).A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC.半导体学报,30(9),66-69.
MLA Yuan Ling,et al."A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC".半导体学报 30.9(2009):66-69.
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