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A novel noise optimization technique for inductively degenerated CMOS LNA
Geng Zhiqing; Wang Haiyong; Wu Nanjian
2009
Source Publication半导体学报
Volume30Issue:10Pages:137-142
AbstractThis paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.
metadata_83institute of semiconductors,chinese academy of sciences
Subject Area半导体物理
Funding Organizationthe National Natural Science Foundation of China,the State Key Development Program for Basic Research of China
Indexed ByCSCD
Language英语
CSCD IDCSCD:3675554
Date Available2010-11-23
Citation statistics
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/15693
Collection中国科学院半导体研究所(2009年前)
Recommended Citation
GB/T 7714
Geng Zhiqing,Wang Haiyong,Wu Nanjian. A novel noise optimization technique for inductively degenerated CMOS LNA[J]. 半导体学报,2009,30(10):137-142.
APA Geng Zhiqing,Wang Haiyong,&Wu Nanjian.(2009).A novel noise optimization technique for inductively degenerated CMOS LNA.半导体学报,30(10),137-142.
MLA Geng Zhiqing,et al."A novel noise optimization technique for inductively degenerated CMOS LNA".半导体学报 30.10(2009):137-142.
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