SEMI OpenIR  > 中国科学院半导体研究所(2009年前)
Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization
Zhou Y; Chen HD; Zuo C; Jia JC; Shen RX; Chen XB; Zhou, Y, Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China.
2005
Conference NameConference on Optical Transmission, Switching and Subsystems II
Source PublicationOptical Transmission Switching and Subsystem II丛书标题: PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)
PagesPts 1 and 2 5625: 933-937 Part 1-2
Conference DateNOV 09-11, 2004
Conference PlaceBeijing, PEOPLES R CHINA
Publication Place1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA
PublisherSPIE-INT SOC OPTICAL ENGINEERING
ISSN0277-786X
ISBN0-8194-5579-2
metadata_83chinese acad sci, inst semicond, state key lab integrated optoelect, beijing 100083, peoples r china
AbstractThis paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.
KeywordVsr
Subject Area光电子学
Funding OrganizationSPIE.; Chinese Opt Soc.; China Inst Commun.
Indexed By其他
Language英语
Document Type会议论文
Identifierhttp://ir.semi.ac.cn/handle/172111/10116
Collection中国科学院半导体研究所(2009年前)
Corresponding AuthorZhou, Y, Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China.
Recommended Citation
GB/T 7714
Zhou Y,Chen HD,Zuo C,et al. Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization[C]. 1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA:SPIE-INT SOC OPTICAL ENGINEERING,2005:Pts 1 and 2 5625: 933-937 Part 1-2.
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